1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a data comparing device for inspecting data stored in a storage device.
2. Description of the Prior Art
In FIG. 16 there is illustrated a conventional data comparing device where a single sense amplifier is provided with respect to a single input data. In the illustration, numeral 1 represents a memory, 1a designates a memory cell for keeping data, 1b depicts a bit line, 1c denotes a bit line (opposition), and 1d is a word line. The data of the memory cell 1a is bidirectionally readable through the respective bit lines 1b and 1c, and the same data read through the bit lines 1b and 1c are in the inverted relation to each other. Further, numeral 2 represents a sense amplifier for sensing the contents of the memory 1, and 2a, 2b respectively indicate input terminals of the sense amplifier 2, i.e., a positive terminal and a negative terminal. In addition, numeral 3 is a sense signal for activating the sense amplifier 2, 4 designates an output terminal of the sense amplifier 2, 6 depicts an output signal of the sense amplifier 2, and 7 denotes an inversion circuit (inverter).
In operation, difficulty is encountered to directly determine the kind (L or H) of the stored data within the memory cell 1a because of a micropotential. Thus, the data is amplified by a sense amplifier. The description will be made hereinbelow in terms of the case that "H" is stored in the memory cell 1a. First, in response to the word line 1d being activated, the content of the memory cell 1a is read out, and "H" is transmitted to the bit line 1b and "L" is transmitted to the bit line 1c. When the sense signal 3 is activated, the sense amplifier 2 decides the "H" level of the bit line 1b and the "L" level of the bit line 1c to output the decision result to the sense amplifier output terminal 4 so that the output signal 6 indicates "H". In the case of requirement of a positive output, the following logic circuit directly derives the output signal 6, and in the case of requirement of a negative output, it derives the output of the inversion circuit 7.
FIG. 17 shows a circuit arrangement where two sense amplifiers are provided. A description will be made hereinbelow only in terms of the different portions between the FIG. 17 circuit arrangement and the FIG. 16 circuit arrangement. The left-side sense amplifier 2 is for deriving the positive output signal and the right-side sense amplifier 2 is for deriving the negative output signal. That is, the left and right output signals 6 are directly derived so as to obtain positive and negative outputs.
In the case that a single sense amplifier 2 is used as illustrated in FIG. 16, in response to the requirement of the opposed output signal (inverted signal) in the following logic circuit, the output signal of the sense amplifier 2 is inverted by the inversion circuit 7 so as to obtain an inverted signal. There is a problem which arises with such an arrangement, however, in that the time is lengthened by an amount corresponding to the operation of the inversion circuit 7 so as to cause the memory access to be delayed as a whole. On the other hand, in the case that two sense amplifiers are used as illustrated in FIG. 17, since the left-side sense amplifier 2 for the positive output signal and the right-side sense amplifier 2 for the negative output signal simultaneously operate, the current value for the left and right-side amplifiers 2 doubles.